HomeCore 0.1.3 (07b5544)
Bare-metal personal computer firmware for Cortex-M
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LM3S6965EVB (QEMU)

Table of Contents

The lm3s6965evb target is the development and regression platform. It runs in QEMU's lm3s6965evb machine, which emulates TI's Stellaris LM3S6965 evaluation board. Every CI run builds it and runs the command regression against it.
QEMU tested in CIEmulator only

The port relies on QEMU's emulated reset state. It does not configure real GPIO, UART baud rates, or a physical oscillator, so physical Stellaris bring-up is not covered.

At a glance
SoCTI LM3S6965 (ti/lm3s6965)
CoreCortex-M3
Flash256 KB at 0x00000000
RAM64 KB at 0x20000000
Clock12.5 MHz reported, no clock setup
ConsoleUART0 through QEMU serial
Presetslm3s6965evb, lm3s6965evb-release

Build and run

cmake --preset lm3s6965evb -DPython3_EXECUTABLE="$PWD/.venv/bin/python"
cmake --build --preset lm3s6965evb
bash scripts/run-qemu-lm3s6965evb.sh

The script boots build/lm3s6965evb/homecore with -nographic. Exit with Ctrl-A, then X. Try help, uptime, cat /dev/uptime, mem, the file commands (also under /ram, a littlefs volume on a 32 KB ramdisk), and reboot. Reboot discards RAM files and the /ram contents and resets the session. See Files and storage.

For the non-interactive regression, run:

python3 tests/qemu_files_test.py

Console and devices

lm3s6965evb QEMU setup QEMU's first serial port connects the host terminal to UART0, which is the HomeCore shell console. UART1 and UART2 are registered as VFS device nodes but do not run shell sessions. Host terminal QEMU -nographic Ctrl-A X exits QEMU machine lm3s6965evb HomeCore firmware /dev/uart0: shell console /dev/uart1, /dev/uart2 registered VFS nodes only reports 12.5 MHz (QEMU reset clock) uptime follows guest virtual time UART0 UART1 UART2

The SoC registers /dev/uart0, /dev/uart1, and /dev/uart2. Standard input, output, and error use UART0. The other nodes are not additional shell sessions.

QEMU's machine has no LED, so /dev/led0 is a console LED (homecore,console-led): each change prints [led0] on or [led0] off, and reads return the last state set. The physical board's status LED on PF0 is not supported. See LEDs.

Clock and uptime

board_cpu_clock_hz() returns 12.5 MHz, which matches QEMU's Stellaris reset divider configuration; see the QEMU model. Uptime follows guest virtual time and stops while emulation is paused. Update the clock reporting if clock setup or physical hardware support is added.

Memory

LM3S6965EVB memory map Flash holds the vector table, code, and the .data load image. RAM holds .data and .bss, including the 32 KB ramdisk, then the heap up to the 3 KB main stack at the top of RAM. Flash · 256 KB 0x0004 0000 0x0000 0000 free .data load image .text, .rodata vector table RAM · 64 KB 0x2001 0000 0x2000 0000 main stack, 3 KB (grows down) heap (grows up) .data, .bss (32 KB ramdisk) Not to scale. The heap is all RAM between .bss and the main stack.

The main stack uses the default CONFIG_HOMECORE_KERNEL_MAIN_STACK_SIZE of 3 KB. mem reports heap use and the stack high-water mark.

Limitations

  • QEMU success verifies this emulated target only. It does not verify STM32 register programming or UART wiring.
  • The port is not suitable for a physical LM3S6965EVB without clock, GPIO, and UART initialization.

The full board guide is docs/boards/lm3s6965evb.md.